1. Field of the Invention
The present invention relates to a multilayer chip capacitor, and a circuit board device including the same.
2. Description of the Related Art
A multilayer chip capacitor is employed as a decoupling capacitor in a large scale integration (LSI) power circuit. Notably, when a power circuit experiences a rapid change in load current, the multilayer chip capacitor serves to suppress voltage noise by supplying current to a central processing unit (CPU) or the like.
In order to suppress noise sufficiently, a decoupling capacitor needs to have low equivalent series inductance (hereinafter, ‘ESL’), and this need has been rising due to the trend toward high-current, high-frequency electronic devices.
Typically, a multilayer chip capacitor includes a capacitor body having a stacked structure of a plurality of dielectric layers, and inner electrodes disposed inside the capacitor body and forming capacitance, and outer electrodes disposed on the outer side of the capacitor body and electrically connected to the inner electrodes. In this case, the smaller the pitch is between the outer electrodes, the lower the ESL value may become. This is because a reduction in the pitch may shorten a current path within the capacitor.
However, a reduction in pitch between outer electrodes may increase the possibility of short-circuit between the outer electrodes of opposite polarity. Outer electrodes may be applied using electroless plating, which allows a pitch between the outer electrodes to be controlled with high precision.